While substantial innovations have been made in packaging semiconductor components and devices, there is a current need for more efficient and economical packaging techniques. For example, the miniaturization and thermal dissipation characteristics of presently available packaging techniques are not adequate to fully take advantage of the inherent performance characteristics of current submicron devices.
Further, with the emergence of very large scale integrated (VLSI) circuits, it becomes necessary for system integration development to package such circuits together so as not to compromise the advancements in circuit integration. Currently, VLSI circuits, such as the one megabit random access memory circuits, are packaged in a plastic or ceramic encapsulant and are available either as a dual inline package or as a leadless chip carrier. Both of these approaches address the packaging problems of single integrated circuit chips, but do not pose solutions to system integration and/or packaging of multiple chips.
From the foregoing, it can be seen that a need exists for an innovative system integration, or packaging technique to complement the corresponding advances in the miniaturization of the device technology. There is an associated need for new packaging apparatus and techniques for integrating together multiple integrated circuit chips in a three dimensional manner so as to provide a highly efficient, economical and compact arrangement, while yet providing adequate thermal dissipation required for densely packed electrical circuits